From 219f63ff4ebb739f349ca3ddd6c11e5068bcf0f1 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Wed, 21 Dec 2022 20:05:58 -0300
Subject: [PATCH] Fix CPU FCVTN instruction implementation (slow path) (#4159)
* Fix CPU FCVTN instruction implementation (slow path)
* PPTC version bump
---
ARMeilleure/Instructions/InstEmitSimdCvt.cs | 4 +---
ARMeilleure/Translation/PTC/Ptc.cs | 2 +-
Ryujinx.Tests/Cpu/CpuTestSimd.cs | 8 ++++----
3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/ARMeilleure/Instructions/InstEmitSimdCvt.cs b/ARMeilleure/Instructions/InstEmitSimdCvt.cs
index 9329f2b75..7f61cad41 100644
--- a/ARMeilleure/Instructions/InstEmitSimdCvt.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdCvt.cs
@@ -381,7 +381,7 @@ namespace ARMeilleure.Instructions
for (int index = 0; index < elems; index++)
{
- Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
+ Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
if (sizeF == 0)
{
@@ -389,8 +389,6 @@ namespace ARMeilleure.Instructions
Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
context.LoadFromContext();
- e = context.ZeroExtend16(OperandType.I64, e);
-
res = EmitVectorInsert(context, res, e, part + index, 1);
}
else /* if (sizeF == 1) */
diff --git a/ARMeilleure/Translation/PTC/Ptc.cs b/ARMeilleure/Translation/PTC/Ptc.cs
index db373bfc9..c2d358c1e 100644
--- a/ARMeilleure/Translation/PTC/Ptc.cs
+++ b/ARMeilleure/Translation/PTC/Ptc.cs
@@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
private const string OuterHeaderMagicString = "PTCohd\0\0";
private const string InnerHeaderMagicString = "PTCihd\0\0";
- private const uint InternalVersion = 4140; //! To be incremented manually for each change to the ARMeilleure project.
+ private const uint InternalVersion = 4159; //! To be incremented manually for each change to the ARMeilleure project.
private const string ActualDir = "0";
private const string BackupDir = "1";
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index be3db0e7b..04110ec37 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -2176,8 +2176,8 @@ namespace Ryujinx.Tests.Cpu
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= ((q & 1) << 30);
- V128 v0 = MakeVectorE0E1(z, z);
- V128 v1 = MakeVectorE0E1(a, a);
+ V128 v0 = MakeVectorE0E1(z, a);
+ V128 v1 = MakeVectorE0E1(a, z);
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
@@ -2202,8 +2202,8 @@ namespace Ryujinx.Tests.Cpu
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= ((q & 1) << 30);
- V128 v0 = MakeVectorE0E1(z, z);
- V128 v1 = MakeVectorE0E1(a, a);
+ V128 v0 = MakeVectorE0E1(z, a);
+ V128 v1 = MakeVectorE0E1(a, z);
SingleOpcode(opcodes, v0: v0, v1: v1);