From d77d691381ffa79b18a0df1b898b20b3a098ca1a Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Wed, 7 Feb 2018 09:38:43 -0300
Subject: [PATCH] Implement SSHL instruction, fix exception on FMAX/FMIN, and
use a better exception message for undefined/unimplemented instructions
---
Ryujinx/Cpu/AOpCodeTable.cs | 1 +
Ryujinx/Cpu/Instruction/AInstEmitException.cs | 2 +-
Ryujinx/Cpu/Instruction/AInstEmitScalar.cs | 17 ++++++++++++++++-
Ryujinx/Cpu/Instruction/AInstEmitSimd.cs | 11 +++++++++--
Ryujinx/Loaders/Executable.cs | 2 --
5 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/Ryujinx/Cpu/AOpCodeTable.cs b/Ryujinx/Cpu/AOpCodeTable.cs
index d15d2e123..1f770c6a1 100644
--- a/Ryujinx/Cpu/AOpCodeTable.cs
+++ b/Ryujinx/Cpu/AOpCodeTable.cs
@@ -208,6 +208,7 @@ namespace ChocolArm64
Set("0x0011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
Set("0x001110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Smax_V, typeof(AOpCodeSimdReg));
Set("0x001110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Smin_V, typeof(AOpCodeSimdReg));
+ Set("0x001110xx1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg));
Set("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
Set("010111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
Set("0x0011110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
diff --git a/Ryujinx/Cpu/Instruction/AInstEmitException.cs b/Ryujinx/Cpu/Instruction/AInstEmitException.cs
index 6e5665fbc..2f1edf781 100644
--- a/Ryujinx/Cpu/Instruction/AInstEmitException.cs
+++ b/Ryujinx/Cpu/Instruction/AInstEmitException.cs
@@ -27,7 +27,7 @@ namespace ChocolArm64.Instruction
public static void Und(AILEmitterCtx Context)
{
- throw new Exception("und inst! " + Context.CurrOp.Position.ToString("x8"));
+ throw new NotImplementedException($"Undefined instruction at {Context.CurrOp.Position:x16}");
}
}
}
\ No newline at end of file
diff --git a/Ryujinx/Cpu/Instruction/AInstEmitScalar.cs b/Ryujinx/Cpu/Instruction/AInstEmitScalar.cs
index fcddb0c98..5085c224e 100644
--- a/Ryujinx/Cpu/Instruction/AInstEmitScalar.cs
+++ b/Ryujinx/Cpu/Instruction/AInstEmitScalar.cs
@@ -498,7 +498,22 @@ namespace ChocolArm64.Instruction
Context.EmitLdvecsf(Op.Rn);
Context.EmitLdvecsf(Op.Rm);
- EmitMathOpCall(Context, Name);
+ MethodInfo MthdInfo;
+
+ if (Op.Size == 0)
+ {
+ MthdInfo = typeof(MathF).GetMethod(Name, new Type[] { typeof(float), typeof(float) });
+ }
+ else if (Op.Size == 1)
+ {
+ MthdInfo = typeof(Math).GetMethod(Name, new Type[] { typeof(double), typeof(double) });
+ }
+ else
+ {
+ throw new InvalidOperationException();
+ }
+
+ Context.EmitCall(MthdInfo);
Context.EmitStvecsf(Op.Rd);
}
diff --git a/Ryujinx/Cpu/Instruction/AInstEmitSimd.cs b/Ryujinx/Cpu/Instruction/AInstEmitSimd.cs
index 0801716ad..c41703bfb 100644
--- a/Ryujinx/Cpu/Instruction/AInstEmitSimd.cs
+++ b/Ryujinx/Cpu/Instruction/AInstEmitSimd.cs
@@ -375,6 +375,8 @@ namespace ChocolArm64.Instruction
public static void Smax_V(AILEmitterCtx Context) => EmitVectorSmax(Context);
public static void Smin_V(AILEmitterCtx Context) => EmitVectorSmin(Context);
+ public static void Sshl_V(AILEmitterCtx Context) => EmitVectorSshl(Context);
+
public static void Sshll_V(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
@@ -737,7 +739,10 @@ namespace ChocolArm64.Instruction
EmitVectorBinarySx(Context, () => Context.EmitCall(MthdInfo));
}
- private static void EmitVectorUshl(AILEmitterCtx Context)
+ private static void EmitVectorSshl(AILEmitterCtx Context) => EmitVectorShl(Context, true);
+ private static void EmitVectorUshl(AILEmitterCtx Context) => EmitVectorShl(Context, false);
+
+ private static void EmitVectorShl(AILEmitterCtx Context, bool Signed)
{
//This instruction shifts the value on vector A by the number of bits
//specified on the signed, lower 8 bits of vector B. If the shift value
@@ -772,7 +777,9 @@ namespace ChocolArm64.Instruction
Context.Emit(OpCodes.Bge_S, LblShl);
Context.Emit(OpCodes.Neg);
- EmitShift(OpCodes.Shr_Un);
+ EmitShift(Signed
+ ? OpCodes.Shr
+ : OpCodes.Shr_Un);
Context.MarkLabel(LblShl);
diff --git a/Ryujinx/Loaders/Executable.cs b/Ryujinx/Loaders/Executable.cs
index 4a3d36f57..785a8c723 100644
--- a/Ryujinx/Loaders/Executable.cs
+++ b/Ryujinx/Loaders/Executable.cs
@@ -7,7 +7,6 @@ namespace Ryujinx.Loaders
{
class Executable
{
- private IExecutable NsoData;
private AMemory Memory;
private ElfDyn[] Dynamic;
@@ -17,7 +16,6 @@ namespace Ryujinx.Loaders
public Executable(IExecutable Exe, AMemory Memory, long ImageBase)
{
- this.NsoData = Exe;
this.Memory = Memory;
this.ImageBase = ImageBase;
this.ImageEnd = ImageBase;