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Gabriel A 2023-12-24 12:58:34 -03:00
parent 1251f03575
commit 339d9ca83d
2 changed files with 9 additions and 15 deletions
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6
src/Ryujinx.Cpu/LightningJit/Arm32/InstDecoders.cs
View File

@ -377,12 +377,6 @@ namespace Ryujinx.Cpu.LightningJit.Arm32
public readonly uint Cond => (_value >> 28) & 0xF; public readonly uint Cond => (_value >> 28) & 0xF;
} }
readonly struct Inst
{
private readonly uint _value;
public Inst(uint value) => _value = value;
}
readonly struct InstCondb28w4Rdb12w4Rmb0w4 readonly struct InstCondb28w4Rdb12w4Rmb0w4
{ {
private readonly uint _value; private readonly uint _value;

18
src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/Assembler.cs
View File

@ -4340,7 +4340,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
WriteInstruction(inst, rt); WriteInstruction(inst, rt);
} }
private void WriteInstructionAuto( private readonly void WriteInstructionAuto(
uint instI, uint instI,
uint instR, uint instR,
Operand rd, Operand rd,
@ -4372,7 +4372,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
} }
} }
private void WriteInstructionAuto( private readonly void WriteInstructionAuto(
uint instR, uint instR,
Operand rd, Operand rd,
Operand rn, Operand rn,
@ -4386,7 +4386,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
WriteInstructionRm16Auto(instR, rd, rn, rm); WriteInstructionRm16Auto(instR, rd, rn, rm);
} }
private void WriteInstructionAuto( private readonly void WriteInstructionAuto(
uint instruction, uint instruction,
Operand rd, Operand rd,
Operand rn, Operand rn,
@ -4402,7 +4402,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
WriteInstructionRm16Auto(instruction, rd, rn, rm); WriteInstructionRm16Auto(instruction, rd, rn, rm);
} }
private void WriteInstructionBitwiseAuto( private readonly void WriteInstructionBitwiseAuto(
uint instI, uint instI,
uint instR, uint instR,
Operand rd, Operand rd,
@ -4426,7 +4426,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
} }
} }
private void WriteInstructionBitwiseAuto( private readonly void WriteInstructionBitwiseAuto(
uint instruction, uint instruction,
Operand rd, Operand rd,
Operand rn, Operand rn,
@ -4445,7 +4445,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
WriteInstructionRm16(instruction, rd, rn, rm); WriteInstructionRm16(instruction, rd, rn, rm);
} }
private void WriteInstructionLdrStrAuto( private readonly void WriteInstructionLdrStrAuto(
uint instruction, uint instruction,
Operand rd, Operand rd,
Operand rn, Operand rn,
@ -4468,7 +4468,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
WriteInstructionRm16(instruction, rd, rn, rm); WriteInstructionRm16(instruction, rd, rn, rm);
} }
private void WriteInstructionAuto(uint instruction, Operand rd) private readonly void WriteInstructionAuto(uint instruction, Operand rd)
{ {
if (rd.Type == OperandType.I64) if (rd.Type == OperandType.I64)
{ {
@ -4488,7 +4488,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
WriteInstruction(instruction, rd, rn); WriteInstruction(instruction, rd, rn);
} }
private void WriteInstructionAuto(uint instruction, Operand rd, Operand rn, Operand rm, Operand ra) private readonly void WriteInstructionAuto(uint instruction, Operand rd, Operand rn, Operand rm, Operand ra)
{ {
if (rd.Type == OperandType.I64) if (rd.Type == OperandType.I64)
{ {
@ -4518,7 +4518,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
WriteUInt32(instruction | EncodeReg(rd) | (EncodeReg(rn) << 5) | (EncodeReg(ra) << 10) | (EncodeReg(rm) << 16)); WriteUInt32(instruction | EncodeReg(rd) | (EncodeReg(rn) << 5) | (EncodeReg(ra) << 10) | (EncodeReg(rm) << 16));
} }
private void WriteInstructionRm16Auto(uint instruction, Operand rd, Operand rn, Operand rm) private readonly void WriteInstructionRm16Auto(uint instruction, Operand rd, Operand rn, Operand rm)
{ {
if (rd.Type == OperandType.I64) if (rd.Type == OperandType.I64)
{ {