forked from MeloNX/MeloNX
427b7d06b5
* Implement a new JIT for Arm devices * Auto-format * Make a lot of Assembler members read-only * More read-only * Fix more warnings * ObjectDisposedException.ThrowIf * New JIT cache for platforms that enforce W^X, currently unused * Remove unused using * Fix assert * Pass memory manager type around * Safe memory manager mode support + other improvements * Actual safe memory manager mode masking support * PR feedback
351 lines
14 KiB
C#
351 lines
14 KiB
C#
using Ryujinx.Cpu.LightningJit.CodeGen;
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using Ryujinx.Cpu.LightningJit.CodeGen.Arm64;
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using System.Diagnostics;
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namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
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{
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static class InstEmitMove
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{
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public static void MvnI(CodeGenContext context, uint rd, uint imm, bool immRotated, bool s)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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if (s)
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{
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using ScopedRegister flagsRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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InstEmitCommon.GetCurrentFlags(context, flagsRegister.Operand);
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if (immRotated)
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{
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if ((imm & (1u << 31)) != 0)
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{
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context.Arm64Assembler.Orr(flagsRegister.Operand, flagsRegister.Operand, InstEmitCommon.Const(1 << 29));
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}
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else
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{
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context.Arm64Assembler.Bfc(flagsRegister.Operand, 29, 1);
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}
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}
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context.Arm64Assembler.Mov(rdOperand, ~imm);
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context.Arm64Assembler.Tst(rdOperand, rdOperand);
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InstEmitCommon.RestoreCvFlags(context, flagsRegister.Operand);
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context.SetNzcvModified();
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}
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else
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{
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context.Arm64Assembler.Mov(rdOperand, ~imm);
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}
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}
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public static void MvnR(CodeGenContext context, uint rd, uint rm, uint sType, uint imm5, bool s)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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ScopedRegister flagsRegister = default;
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if (s)
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{
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flagsRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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InstEmitCommon.GetCurrentFlags(context, flagsRegister.Operand);
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rmOperand = InstEmitAlu.GetMShiftedByImmediate(context, tempRegister.Operand, rmOperand, imm5, sType, flagsRegister.Operand);
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}
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else
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{
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rmOperand = InstEmitAlu.GetMShiftedByImmediate(context, tempRegister.Operand, rmOperand, imm5, sType);
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}
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context.Arm64Assembler.Mvn(rdOperand, rmOperand);
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if (s)
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{
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InstEmitCommon.RestoreCvFlags(context, flagsRegister.Operand);
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flagsRegister.Dispose();
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context.SetNzcvModified();
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}
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}
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public static void MvnRr(CodeGenContext context, uint rd, uint rm, uint sType, uint rs, bool s)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
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Operand rsOperand = InstEmitCommon.GetInputGpr(context, rs);
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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ScopedRegister flagsRegister = default;
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if (s)
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{
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flagsRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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InstEmitCommon.GetCurrentFlags(context, flagsRegister.Operand);
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rmOperand = InstEmitAlu.GetMShiftedByReg(context, tempRegister.Operand, rmOperand, rsOperand, sType, flagsRegister.Operand);
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}
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else
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{
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rmOperand = InstEmitAlu.GetMShiftedByReg(context, tempRegister.Operand, rmOperand, rsOperand, sType);
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}
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context.Arm64Assembler.Mvn(rdOperand, rmOperand);
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if (s)
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{
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InstEmitCommon.RestoreCvFlags(context, flagsRegister.Operand);
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flagsRegister.Dispose();
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context.SetNzcvModified();
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}
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}
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public static void MovI(CodeGenContext context, uint rd, uint imm, bool immRotated, bool s)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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if (s)
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{
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using ScopedRegister flagsRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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InstEmitCommon.GetCurrentFlags(context, flagsRegister.Operand);
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if (immRotated)
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{
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if ((imm & (1u << 31)) != 0)
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{
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context.Arm64Assembler.Orr(flagsRegister.Operand, flagsRegister.Operand, InstEmitCommon.Const(2));
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}
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else
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{
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context.Arm64Assembler.Bfc(flagsRegister.Operand, 1, 1);
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}
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}
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context.Arm64Assembler.Mov(rdOperand, imm);
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context.Arm64Assembler.Tst(rdOperand, rdOperand);
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InstEmitCommon.RestoreCvFlags(context, flagsRegister.Operand);
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context.SetNzcvModified();
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}
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else
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{
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context.Arm64Assembler.Mov(rdOperand, imm);
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}
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}
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public static void MovR(CodeGenContext context, uint rd, uint rm, uint sType, uint imm5, bool s)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
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if (InstEmitAlu.CanShift(sType, imm5) && !s)
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{
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if (imm5 != 0)
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{
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switch ((ArmShiftType)sType)
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{
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case ArmShiftType.Lsl:
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context.Arm64Assembler.Lsl(rdOperand, rmOperand, InstEmitCommon.Const((int)imm5));
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break;
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case ArmShiftType.Lsr:
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context.Arm64Assembler.Lsr(rdOperand, rmOperand, InstEmitCommon.Const((int)imm5));
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break;
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case ArmShiftType.Asr:
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context.Arm64Assembler.Asr(rdOperand, rmOperand, InstEmitCommon.Const((int)imm5));
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break;
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case ArmShiftType.Ror:
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context.Arm64Assembler.Ror(rdOperand, rmOperand, InstEmitCommon.Const((int)imm5));
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break;
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}
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}
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else
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{
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context.Arm64Assembler.Mov(rdOperand, rmOperand);
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}
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}
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else
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{
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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ScopedRegister flagsRegister = default;
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if (s)
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{
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flagsRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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InstEmitCommon.GetCurrentFlags(context, flagsRegister.Operand);
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rmOperand = InstEmitAlu.GetMShiftedByImmediate(context, tempRegister.Operand, rmOperand, imm5, sType, flagsRegister.Operand);
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}
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else
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{
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rmOperand = InstEmitAlu.GetMShiftedByImmediate(context, tempRegister.Operand, rmOperand, imm5, sType, null);
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}
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context.Arm64Assembler.Mov(rdOperand, rmOperand);
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if (s)
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{
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context.Arm64Assembler.Tst(rdOperand, rdOperand);
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InstEmitCommon.RestoreCvFlags(context, flagsRegister.Operand);
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flagsRegister.Dispose();
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context.SetNzcvModified();
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}
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}
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}
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public static void MovR(CodeGenContext context, uint cond, uint rd, uint rm, uint sType, uint imm5, bool s)
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{
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if (context.ConsumeSkipNextInstruction())
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{
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return;
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}
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if ((ArmCondition)cond >= ArmCondition.Al || s)
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{
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MovR(context, rd, rm, sType, imm5, s);
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return;
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}
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
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if (InstEmitAlu.CanShift(sType, imm5))
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{
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if (imm5 != 0)
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{
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switch ((ArmShiftType)sType)
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{
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case ArmShiftType.Lsl:
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context.Arm64Assembler.Lsl(tempRegister.Operand, rmOperand, InstEmitCommon.Const((int)imm5));
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break;
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case ArmShiftType.Lsr:
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context.Arm64Assembler.Lsr(tempRegister.Operand, rmOperand, InstEmitCommon.Const((int)imm5));
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break;
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case ArmShiftType.Asr:
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context.Arm64Assembler.Asr(tempRegister.Operand, rmOperand, InstEmitCommon.Const((int)imm5));
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break;
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case ArmShiftType.Ror:
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context.Arm64Assembler.Ror(tempRegister.Operand, rmOperand, InstEmitCommon.Const((int)imm5));
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break;
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}
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context.Arm64Assembler.Csel(rdOperand, tempRegister.Operand, rdOperand, (ArmCondition)cond);
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}
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else
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{
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Operand other = rdOperand;
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InstInfo nextInstruction = context.PeekNextInstruction();
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if (nextInstruction.Name == InstName.MovR)
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{
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// If this instruction is followed by another move with the inverse condition,
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// we can just put it into the second operand of the CSEL instruction and skip the next move.
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InstCondb28w4Sb20w1Rdb12w4Imm5b7w5Stypeb5w2Rmb0w4 nextInst = new(nextInstruction.Encoding);
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if (nextInst.Rd == rd &&
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nextInst.S == 0 &&
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nextInst.Stype == 0 &&
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nextInst.Imm5 == 0 &&
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nextInst.Cond == (cond ^ 1u) &&
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nextInst.Rm != RegisterUtils.PcRegister)
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{
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other = InstEmitCommon.GetInputGpr(context, nextInst.Rm);
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context.SetSkipNextInstruction();
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}
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}
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context.Arm64Assembler.Csel(rdOperand, rmOperand, other, (ArmCondition)cond);
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}
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}
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else
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{
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rmOperand = InstEmitAlu.GetMShiftedByImmediate(context, tempRegister.Operand, rmOperand, imm5, sType, null);
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context.Arm64Assembler.Csel(rdOperand, rmOperand, rdOperand, (ArmCondition)cond);
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}
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}
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public static void MovRr(CodeGenContext context, uint rd, uint rm, uint sType, uint rs, bool s)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
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Operand rsOperand = InstEmitCommon.GetInputGpr(context, rs);
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if (!s)
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{
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InstEmitAlu.GetMShiftedByReg(context, rdOperand, rmOperand, rsOperand, sType);
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}
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else
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{
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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using ScopedRegister flagsRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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InstEmitCommon.GetCurrentFlags(context, flagsRegister.Operand);
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rmOperand = InstEmitAlu.GetMShiftedByReg(context, tempRegister.Operand, rmOperand, rsOperand, sType, flagsRegister.Operand);
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context.Arm64Assembler.Mov(rdOperand, rmOperand);
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context.Arm64Assembler.Tst(rdOperand, rdOperand);
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InstEmitCommon.RestoreCvFlags(context, flagsRegister.Operand);
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context.SetNzcvModified();
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}
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}
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public static void Movt(CodeGenContext context, uint rd, uint imm)
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{
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Operand rdOperand = InstEmitCommon.GetInputGpr(context, rd);
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context.Arm64Assembler.Movk(rdOperand, (int)imm, 1);
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}
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public static void Pkh(CodeGenContext context, uint rd, uint rn, uint rm, bool tb, uint imm5)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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Operand rnOperand = InstEmitCommon.GetInputGpr(context, rn);
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Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
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if (!tb && imm5 == 0)
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{
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context.Arm64Assembler.Extr(rdOperand, rnOperand, rmOperand, 16);
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}
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else
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{
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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if (tb)
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{
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context.Arm64Assembler.Asr(tempRegister.Operand, rmOperand, InstEmitCommon.Const(imm5 == 0 ? 31 : (int)imm5));
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context.Arm64Assembler.Extr(rdOperand, tempRegister.Operand, rnOperand, 16);
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}
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else
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{
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context.Arm64Assembler.Lsl(tempRegister.Operand, rmOperand, InstEmitCommon.Const((int)imm5));
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context.Arm64Assembler.Extr(rdOperand, rnOperand, tempRegister.Operand, 16);
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}
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}
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context.Arm64Assembler.Ror(rdOperand, rdOperand, InstEmitCommon.Const(16));
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}
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}
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}
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