forked from MeloNX/MeloNX
9288ffd26d
* cpu: Implement VCVT (between floating-point and fixed-point) instruction Rebase, fix and superseed of https://github.com/Ryujinx/Ryujinx/pull/2915 (Since I only have little CPU knowledge, I hope I have done everything good) * Update Ptc.cs * Fix wrong cast * Rename tests * Addresses feedback Co-Authored-By: gdkchan <5624669+gdkchan@users.noreply.github.com> * Remove extra empty line --------- Co-authored-by: gdkchan <5624669+gdkchan@users.noreply.github.com>
23 lines
880 B
C#
23 lines
880 B
C#
namespace ARMeilleure.Decoders
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{
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class OpCode32SimdCvtFFixed : OpCode32Simd
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{
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public int Fbits { get; protected set; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFFixed(inst, address, opCode, false);
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public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFFixed(inst, address, opCode, true);
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public OpCode32SimdCvtFFixed(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
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{
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Opc = (opCode >> 8) & 0x1;
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Size = Opc == 1 ? 0 : 2;
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Fbits = 64 - ((opCode >> 16) & 0x3f);
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if (DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vm))
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{
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Instruction = InstDescriptor.Undefined;
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}
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}
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}
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} |