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ARMeilleure: replace else-ifs with switch statements #124

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LukeWarnut wants to merge 1 commits from switch-st into master
pull from: switch-st
merge into: MeloNX:master
Conversation 8 Commits 1 Files Changed 20 +675 -651
20 changed files with 675 additions and 651 deletions
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13
src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs
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@ -1445,16 +1445,15 @@ namespace ARMeilleure.CodeGen.Arm64
return false; return false;
} }
if (currentOp.Instruction == Instruction.Load) switch (currentOp.Instruction)
{ {
case Instruction.Load:
context.Assembler.LdpRiUn(currentOp.Destination, nextOp.Destination, op1Base, op1Offset); context.Assembler.LdpRiUn(currentOp.Destination, nextOp.Destination, op1Base, op1Offset);
} break;
else if (currentOp.Instruction == Instruction.Store) case Instruction.Store:
{
context.Assembler.StpRiUn(currentOp.GetSource(1), nextOp.GetSource(1), op1Base, op1Offset); context.Assembler.StpRiUn(currentOp.GetSource(1), nextOp.GetSource(1), op1Base, op1Offset);
} break;
else default:
{
return false; return false;
} }

11
src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs
View File

@ -1099,16 +1099,13 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
private static int GetOperandId(Operand operand) private static int GetOperandId(Operand operand)
{ {
if (operand.Kind == OperandKind.LocalVariable) switch (operand.Kind)
{ {
case OperandKind.LocalVariable:
return operand.GetLocalNumber(); return operand.GetLocalNumber();
} case OperandKind.Register:
else if (operand.Kind == OperandKind.Register)
{
return GetRegisterId(operand.GetRegister()); return GetRegisterId(operand.GetRegister());
} default:
else
{
throw new ArgumentException($"Invalid operand kind \"{operand.Kind}\"."); throw new ArgumentException($"Invalid operand kind \"{operand.Kind}\".");
} }
} }

11
src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs
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@ -33,16 +33,13 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
public int GetAvailableRegisters(RegisterType type) public int GetAvailableRegisters(RegisterType type)
{ {
if (type == RegisterType.Integer) switch (type)
{ {
case RegisterType.Integer:
return IntAvailableRegisters; return IntAvailableRegisters;
} case RegisterType.Vector:
else if (type == RegisterType.Vector)
{
return VecAvailableRegisters; return VecAvailableRegisters;
} default:
else
{
throw new ArgumentException($"Invalid register type \"{type}\"."); throw new ArgumentException($"Invalid register type \"{type}\".");
} }
} }

69
src/ARMeilleure/CodeGen/X86/Assembler.cs
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@ -754,8 +754,9 @@ namespace ARMeilleure.CodeGen.X86
if (source != default) if (source != default)
{ {
if (source.Kind == OperandKind.Constant) switch (source.Kind)
{ {
case OperandKind.Constant:
ulong imm = source.Value; ulong imm = source.Value;
if (inst == X86Instruction.Mov8) if (inst == X86Instruction.Mov8)
@ -809,12 +810,14 @@ namespace ARMeilleure.CodeGen.X86
{ {
throw new ArgumentException($"Failed to encode constant 0x{imm:X}."); throw new ArgumentException($"Failed to encode constant 0x{imm:X}.");
} }
}
else if (source.Kind == OperandKind.Register && info.OpRMR != BadOp) break;
{
case OperandKind.Register when info.OpRMR != BadOp:
WriteOpCode(dest, default, source, type, info.Flags, info.OpRMR); WriteOpCode(dest, default, source, type, info.Flags, info.OpRMR);
} break;
else if (info.OpRRM != BadOp) default:
if (info.OpRRM != BadOp)
{ {
WriteOpCode(dest, default, source, type, info.Flags, info.OpRRM, rrm: true); WriteOpCode(dest, default, source, type, info.Flags, info.OpRRM, rrm: true);
} }
@ -822,6 +825,9 @@ namespace ARMeilleure.CodeGen.X86
{ {
throw new ArgumentException($"Invalid source operand kind \"{source.Kind}\"."); throw new ArgumentException($"Invalid source operand kind \"{source.Kind}\".");
} }
break;
}
} }
else if (info.OpRRM != BadOp) else if (info.OpRRM != BadOp)
{ {
@ -848,8 +854,9 @@ namespace ARMeilleure.CodeGen.X86
if (src2 != default) if (src2 != default)
{ {
if (src2.Kind == OperandKind.Constant) switch (src2.Kind)
{ {
case OperandKind.Constant:
ulong imm = src2.Value; ulong imm = src2.Value;
if ((byte)imm == imm && info.OpRMImm8 != BadOp) if ((byte)imm == imm && info.OpRMImm8 != BadOp)
@ -862,12 +869,15 @@ namespace ARMeilleure.CodeGen.X86
{ {
throw new ArgumentException($"Failed to encode constant 0x{imm:X}."); throw new ArgumentException($"Failed to encode constant 0x{imm:X}.");
} }
}
else if (src2.Kind == OperandKind.Register && info.OpRMR != BadOp) break;
{
case OperandKind.Register when info.OpRMR != BadOp:
WriteOpCode(dest, src1, src2, type, info.Flags, info.OpRMR); WriteOpCode(dest, src1, src2, type, info.Flags, info.OpRMR);
} break;
else if (info.OpRRM != BadOp)
default:
if (info.OpRRM != BadOp)
{ {
WriteOpCode(dest, src1, src2, type, info.Flags, info.OpRRM, rrm: true); WriteOpCode(dest, src1, src2, type, info.Flags, info.OpRRM, rrm: true);
} }
@ -875,6 +885,9 @@ namespace ARMeilleure.CodeGen.X86
{ {
throw new ArgumentException($"Invalid source operand kind \"{src2.Kind}\"."); throw new ArgumentException($"Invalid source operand kind \"{src2.Kind}\".");
} }
break;
}
} }
else if (info.OpRRM != BadOp) else if (info.OpRRM != BadOp)
{ {
@ -913,8 +926,9 @@ namespace ARMeilleure.CodeGen.X86
if (dest != default) if (dest != default)
{ {
if (dest.Kind == OperandKind.Register) switch (dest.Kind)
{ {
case OperandKind.Register:
int regIndex = dest.GetRegister().Index; int regIndex = dest.GetRegister().Index;
modRM |= (regIndex & 0b111) << (rrm ? 3 : 0); modRM |= (regIndex & 0b111) << (rrm ? 3 : 0);
@ -923,22 +937,24 @@ namespace ARMeilleure.CodeGen.X86
{ {
rexPrefix |= RexPrefix; rexPrefix |= RexPrefix;
} }
}
else if (dest.Kind == OperandKind.Memory) break;
{
case OperandKind.Memory:
memOp = dest.GetMemory(); memOp = dest.GetMemory();
hasMemOp = true; hasMemOp = true;
} break;
else
{ default:
throw new ArgumentException("Invalid destination operand kind \"" + dest.Kind + "\"."); throw new ArgumentException("Invalid destination operand kind \"" + dest.Kind + "\".");
} }
} }
if (src2 != default) if (src2 != default)
{ {
if (src2.Kind == OperandKind.Register) switch (src2.Kind)
{ {
case OperandKind.Register:
int regIndex = src2.GetRegister().Index; int regIndex = src2.GetRegister().Index;
modRM |= (regIndex & 0b111) << (rrm ? 0 : 3); modRM |= (regIndex & 0b111) << (rrm ? 0 : 3);
@ -947,14 +963,15 @@ namespace ARMeilleure.CodeGen.X86
{ {
rexPrefix |= RexPrefix; rexPrefix |= RexPrefix;
} }
}
else if (src2.Kind == OperandKind.Memory && !hasMemOp) break;
{
case OperandKind.Memory when !hasMemOp:
memOp = src2.GetMemory(); memOp = src2.GetMemory();
hasMemOp = true; hasMemOp = true;
} break;
else
{ default:
throw new ArgumentException("Invalid source operand kind \"" + src2.Kind + "\"."); throw new ArgumentException("Invalid source operand kind \"" + src2.Kind + "\".");
} }
} }

38
src/ARMeilleure/CodeGen/X86/CodeGenerator.cs
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@ -423,25 +423,24 @@ namespace ARMeilleure.CodeGen.X86
Debug.Assert(!dest.Type.IsInteger()); Debug.Assert(!dest.Type.IsInteger());
if (info.Inst == X86Instruction.Blendvpd && HardwareCapabilities.SupportsVexEncoding) switch (info.Inst)
{ {
case X86Instruction.Blendvpd when HardwareCapabilities.SupportsVexEncoding:
context.Assembler.WriteInstruction(X86Instruction.Vblendvpd, dest, src1, src2, src3); context.Assembler.WriteInstruction(X86Instruction.Vblendvpd, dest, src1, src2, src3);
} break;
else if (info.Inst == X86Instruction.Blendvps && HardwareCapabilities.SupportsVexEncoding) case X86Instruction.Blendvps when HardwareCapabilities.SupportsVexEncoding:
{
context.Assembler.WriteInstruction(X86Instruction.Vblendvps, dest, src1, src2, src3); context.Assembler.WriteInstruction(X86Instruction.Vblendvps, dest, src1, src2, src3);
} break;
else if (info.Inst == X86Instruction.Pblendvb && HardwareCapabilities.SupportsVexEncoding) case X86Instruction.Pblendvb when HardwareCapabilities.SupportsVexEncoding:
{
context.Assembler.WriteInstruction(X86Instruction.Vpblendvb, dest, src1, src2, src3); context.Assembler.WriteInstruction(X86Instruction.Vpblendvb, dest, src1, src2, src3);
} break;
else default:
{
EnsureSameReg(dest, src1); EnsureSameReg(dest, src1);
Debug.Assert(src3.GetRegister().Index == 0); Debug.Assert(src3.GetRegister().Index == 0);
context.Assembler.WriteInstruction(info.Inst, dest, src1, src2); context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
break;
} }
break; break;
@ -1406,8 +1405,9 @@ namespace ARMeilleure.CodeGen.X86
} }
} }
if (src2.Type == OperandType.I32) switch (src2.Type)
{ {
case OperandType.I32:
Debug.Assert(index < 4); Debug.Assert(index < 4);
if (HardwareCapabilities.SupportsSse41) if (HardwareCapabilities.SupportsSse41)
@ -1418,9 +1418,8 @@ namespace ARMeilleure.CodeGen.X86
{ {
InsertIntSse2(2); InsertIntSse2(2);
} }
} break;
else if (src2.Type == OperandType.I64) case OperandType.I64:
{
Debug.Assert(index < 2); Debug.Assert(index < 2);
if (HardwareCapabilities.SupportsSse41) if (HardwareCapabilities.SupportsSse41)
@ -1431,8 +1430,8 @@ namespace ARMeilleure.CodeGen.X86
{ {
InsertIntSse2(4); InsertIntSse2(4);
} }
} break;
else if (src2.Type == OperandType.FP32) case OperandType.FP32:
{ {
Debug.Assert(index < 4); Debug.Assert(index < 4);
@ -1475,9 +1474,11 @@ namespace ARMeilleure.CodeGen.X86
{ {
context.Assembler.Movss(dest, src1, src2); context.Assembler.Movss(dest, src1, src2);
} }
break;
} }
else /* if (src2.Type == OperandType.FP64) */
{ default:
Debug.Assert(index < 2); Debug.Assert(index < 2);
if (index != 0) if (index != 0)
@ -1488,6 +1489,7 @@ namespace ARMeilleure.CodeGen.X86
{ {
context.Assembler.Movsd(dest, src1, src2); context.Assembler.Movsd(dest, src1, src2);
} }
break;
} }
} }

13
src/ARMeilleure/CodeGen/X86/X86Optimizer.cs
View File

@ -141,18 +141,17 @@ namespace ARMeilleure.CodeGen.X86
Operand constOp; Operand constOp;
Operand otherOp; Operand otherOp;
if (src1.Kind == OperandKind.Constant && src2.Kind == OperandKind.LocalVariable) switch (src1.Kind)
{ {
case OperandKind.Constant when src2.Kind == OperandKind.LocalVariable:
constOp = src1; constOp = src1;
otherOp = src2; otherOp = src2;
} break;
else if (src1.Kind == OperandKind.LocalVariable && src2.Kind == OperandKind.Constant) case OperandKind.LocalVariable when src2.Kind == OperandKind.Constant:
{
constOp = src2; constOp = src2;
otherOp = src1; otherOp = src1;
} break;
else default:
{
return 0; return 0;
} }

19
src/ARMeilleure/Decoders/OpCodeAluImm.cs
View File

@ -10,16 +10,17 @@ namespace ARMeilleure.Decoders
public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{ {
if (DataOp == DataOp.Arithmetic) switch (DataOp)
{ {
Immediate = (opCode >> 10) & 0xfff; case DataOp.Arithmetic:
Immediate = opCode >> 10 & 0xfff;
int shift = (opCode >> 22) & 3; int shift = opCode >> 22 & 3;
Immediate <<= shift * 12; Immediate <<= shift * 12;
} break;
else if (DataOp == DataOp.Logical)
{ case DataOp.Logical:
var bm = DecoderHelper.DecodeBitMask(opCode, true); var bm = DecoderHelper.DecodeBitMask(opCode, true);
if (bm.IsUndefined) if (bm.IsUndefined)
@ -30,9 +31,9 @@ namespace ARMeilleure.Decoders
} }
Immediate = bm.WMask; Immediate = bm.WMask;
} break;
else
{ default:
throw new ArgumentException($"Invalid data operation: {DataOp}", nameof(opCode)); throw new ArgumentException($"Invalid data operation: {DataOp}", nameof(opCode));
} }
} }

27
src/ARMeilleure/Decoders/OpCodeTable.cs
View File

@ -1438,28 +1438,29 @@ namespace ARMeilleure.Decoders
// but 00 isn't. // but 00 isn't.
char chr = encoding[index]; char chr = encoding[index];
if (chr == '1') switch (chr)
{ {
case '1':
value |= 1 << bit; value |= 1 << bit;
} break;
else if (chr == 'x') case 'x':
{
xMask |= 1 << bit; xMask |= 1 << bit;
} break;
else if (chr == '>') case '>':
{
xPos[xBits++] = bit; xPos[xBits++] = bit;
} break;
else if (chr == '<') case '<':
{
xPos[xBits++] = bit; xPos[xBits++] = bit;
blacklisted |= 1 << bit; blacklisted |= 1 << bit;
} break;
else if (chr != '0') default:
if (chr != '0')
{ {
throw new ArgumentException($"Invalid encoding: {encoding}", nameof(encoding)); throw new ArgumentException($"Invalid encoding: {encoding}", nameof(encoding));
} }
break;
}
} }
xMask = ~xMask; xMask = ~xMask;

14
src/ARMeilleure/Instructions/InstEmitAlu32.cs
View File

@ -1214,17 +1214,17 @@ namespace ARMeilleure.Instructions
elementAction(tempD, nByte, mByte); elementAction(tempD, nByte, mByte);
if (b == 0) switch (b)
{ {
case 0:
result = context.ZeroExtend8(OperandType.I32, tempD); result = context.ZeroExtend8(OperandType.I32, tempD);
} break;
else if (b < 3) case < 3:
{
result = context.BitwiseOr(result, context.ShiftLeft(context.ZeroExtend8(OperandType.I32, tempD), Const(b * 8))); result = context.BitwiseOr(result, context.ShiftLeft(context.ZeroExtend8(OperandType.I32, tempD), Const(b * 8)));
} break;
else default:
{
result = context.BitwiseOr(result, context.ShiftLeft(tempD, Const(24))); result = context.BitwiseOr(result, context.ShiftLeft(tempD, Const(24)));
break;
} }
} }

13
src/ARMeilleure/Instructions/InstEmitMemoryEx.cs
View File

@ -69,7 +69,9 @@ namespace ARMeilleure.Instructions
// read all the data at once. For a 32-bits pairwise load, we do a // read all the data at once. For a 32-bits pairwise load, we do a
// simple 64-bits load, for a 128-bits load, we need to call a special // simple 64-bits load, for a 128-bits load, we need to call a special
// method to read 128-bits atomically. // method to read 128-bits atomically.
if (op.Size == 2) switch (op.Size)
{
case 2:
{ {
Operand value = EmitLoadExclusive(context, address, exclusive, 3); Operand value = EmitLoadExclusive(context, address, exclusive, 3);
@ -81,8 +83,10 @@ namespace ARMeilleure.Instructions
SetIntOrZR(context, op.Rt, valueLow); SetIntOrZR(context, op.Rt, valueLow);
SetIntOrZR(context, op.Rt2, valueHigh); SetIntOrZR(context, op.Rt2, valueHigh);
break;
} }
else if (op.Size == 3)
case 3:
{ {
Operand value = EmitLoadExclusive(context, address, exclusive, 4); Operand value = EmitLoadExclusive(context, address, exclusive, 4);
@ -91,9 +95,10 @@ namespace ARMeilleure.Instructions
SetIntOrZR(context, op.Rt, valueLow); SetIntOrZR(context, op.Rt, valueLow);
SetIntOrZR(context, op.Rt2, valueHigh); SetIntOrZR(context, op.Rt2, valueHigh);
break;
} }
else
{ default:
throw new InvalidOperationException($"Invalid load size of {1 << op.Size} bytes."); throw new InvalidOperationException($"Invalid load size of {1 << op.Size} bytes.");
} }
} }

14
src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs
View File

@ -338,17 +338,17 @@ namespace ARMeilleure.Instructions
value = context.ConvertI64ToI32(value); value = context.ConvertI64ToI32(value);
} }
if (size == 0) switch (size)
{ {
case 0:
context.Store8(physAddr, value); context.Store8(physAddr, value);
} break;
else if (size == 1) case 1:
{
context.Store16(physAddr, value); context.Store16(physAddr, value);
} break;
else default:
{
context.Store(physAddr, value); context.Store(physAddr, value);
break;
} }
} }

22
src/ARMeilleure/Instructions/InstEmitSimdMove.cs
View File

@ -100,8 +100,9 @@ namespace ARMeilleure.Instructions
{ {
Operand res = GetVec(op.Rn); Operand res = GetVec(op.Rn);
if (op.Size == 0) switch (op.Size)
{ {
case 0:
if (op.DstIndex != 0) if (op.DstIndex != 0)
{ {
res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(op.DstIndex)); res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(op.DstIndex));
@ -110,9 +111,9 @@ namespace ARMeilleure.Instructions
res = context.AddIntrinsic(Intrinsic.X86Punpcklbw, res, res); res = context.AddIntrinsic(Intrinsic.X86Punpcklbw, res, res);
res = context.AddIntrinsic(Intrinsic.X86Punpcklwd, res, res); res = context.AddIntrinsic(Intrinsic.X86Punpcklwd, res, res);
res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0)); res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0));
} break;
else if (op.Size == 1)
{ case 1:
if (op.DstIndex != 0) if (op.DstIndex != 0)
{ {
res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(op.DstIndex * 2)); res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(op.DstIndex * 2));
@ -120,14 +121,18 @@ namespace ARMeilleure.Instructions
res = context.AddIntrinsic(Intrinsic.X86Punpcklwd, res, res); res = context.AddIntrinsic(Intrinsic.X86Punpcklwd, res, res);
res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0)); res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0));
} break;
else if (op.Size == 2)
case 2:
{ {
int mask = op.DstIndex * 0b01010101; int mask = op.DstIndex * 0b01010101;
res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(mask)); res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(mask));
break;
} }
else if (op.DstIndex == 0 && op.RegisterSize != RegisterSize.Simd64)
default:
if (op.DstIndex == 0 && op.RegisterSize != RegisterSize.Simd64)
{ {
res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, res); res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, res);
} }
@ -136,6 +141,9 @@ namespace ARMeilleure.Instructions
res = context.AddIntrinsic(Intrinsic.X86Movhlps, res, res); res = context.AddIntrinsic(Intrinsic.X86Movhlps, res, res);
} }
break;
}
if (op.RegisterSize == RegisterSize.Simd64) if (op.RegisterSize == RegisterSize.Simd64)
{ {
res = context.VectorZeroUpper64(res); res = context.VectorZeroUpper64(res);

32
src/ARMeilleure/Instructions/InstEmitSimdShift32.cs
View File

@ -221,17 +221,18 @@ namespace ARMeilleure.Instructions
if (op.U) if (op.U)
{ {
if (op.Size < 2) switch (op.Size)
{ {
case < 2:
EmitVectorUnaryOpZx32(context, (op1) => EmitVectorUnaryOpZx32(context, (op1) =>
{ {
op1 = context.Add(op1, Const(op1.Type, roundConst)); op1 = context.Add(op1, Const(op1.Type, roundConst));
return context.ShiftRightUI(op1, Const(shift)); return context.ShiftRightUI(op1, Const(shift));
}, accumulate); }, accumulate);
} break;
else if (op.Size == 2)
{ case 2:
EmitVectorUnaryOpZx32(context, (op1) => EmitVectorUnaryOpZx32(context, (op1) =>
{ {
op1 = context.ZeroExtend32(OperandType.I64, op1); op1 = context.ZeroExtend32(OperandType.I64, op1);
@ -239,25 +240,29 @@ namespace ARMeilleure.Instructions
return context.ConvertI64ToI32(context.ShiftRightUI(op1, Const(shift))); return context.ConvertI64ToI32(context.ShiftRightUI(op1, Const(shift)));
}, accumulate); }, accumulate);
} break;
else /* if (op.Size == 3) */
default: // case 3
{ {
EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: false, roundConst, shift), accumulate); EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: false, roundConst, shift), accumulate);
break;
}
} }
} }
else else
{ {
if (op.Size < 2) switch (op.Size)
{ {
case < 2:
EmitVectorUnaryOpSx32(context, (op1) => EmitVectorUnaryOpSx32(context, (op1) =>
{ {
op1 = context.Add(op1, Const(op1.Type, roundConst)); op1 = context.Add(op1, Const(op1.Type, roundConst));
return context.ShiftRightSI(op1, Const(shift)); return context.ShiftRightSI(op1, Const(shift));
}, accumulate); }, accumulate);
} break;
else if (op.Size == 2)
{ case 2:
EmitVectorUnaryOpSx32(context, (op1) => EmitVectorUnaryOpSx32(context, (op1) =>
{ {
op1 = context.SignExtend32(OperandType.I64, op1); op1 = context.SignExtend32(OperandType.I64, op1);
@ -265,10 +270,11 @@ namespace ARMeilleure.Instructions
return context.ConvertI64ToI32(context.ShiftRightSI(op1, Const(shift))); return context.ConvertI64ToI32(context.ShiftRightSI(op1, Const(shift)));
}, accumulate); }, accumulate);
} break;
else /* if (op.Size == 3) */
{ default: // case 3
EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: true, roundConst, shift), accumulate); EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: true, roundConst, shift), accumulate);
break;
} }
} }
} }

99
src/ARMeilleure/Instructions/SoftFloat.cs
View File

@ -495,8 +495,10 @@ namespace ARMeilleure.Instructions
double result; double result;
if (type == FPType.SNaN || type == FPType.QNaN) switch (type)
{ {
case FPType.SNaN:
case FPType.QNaN:
if ((context.Fpcr & FPCR.Dn) != 0) if ((context.Fpcr & FPCR.Dn) != 0)
{ {
result = SoftFloat64.FPDefaultNaN(); result = SoftFloat64.FPDefaultNaN();
@ -510,18 +512,16 @@ namespace ARMeilleure.Instructions
{ {
SoftFloat.FPProcessException(FPException.InvalidOp, context); SoftFloat.FPProcessException(FPException.InvalidOp, context);
} }
} break;
else if (type == FPType.Infinity) case FPType.Infinity:
{
result = SoftFloat64.FPInfinity(sign); result = SoftFloat64.FPInfinity(sign);
} break;
else if (type == FPType.Zero) case FPType.Zero:
{
result = SoftFloat64.FPZero(sign); result = SoftFloat64.FPZero(sign);
} break;
else default:
{
result = FPRoundCv(real, context); result = FPRoundCv(real, context);
break;
} }
return result; return result;
@ -672,8 +672,10 @@ namespace ARMeilleure.Instructions
ushort resultBits; ushort resultBits;
if (type == FPType.SNaN || type == FPType.QNaN) switch (type)
{ {
case FPType.SNaN:
case FPType.QNaN:
if (altHp) if (altHp)
{ {
resultBits = SoftFloat16.FPZero(sign); resultBits = SoftFloat16.FPZero(sign);
@ -691,9 +693,9 @@ namespace ARMeilleure.Instructions
{ {
SoftFloat.FPProcessException(FPException.InvalidOp, context); SoftFloat.FPProcessException(FPException.InvalidOp, context);
} }
} break;
else if (type == FPType.Infinity)
{ case FPType.Infinity:
if (altHp) if (altHp)
{ {
resultBits = (ushort)((sign ? 1u : 0u) << 15 | 0x7FFFu); resultBits = (ushort)((sign ? 1u : 0u) << 15 | 0x7FFFu);
@ -704,14 +706,15 @@ namespace ARMeilleure.Instructions
{ {
resultBits = SoftFloat16.FPInfinity(sign); resultBits = SoftFloat16.FPInfinity(sign);
} }
} break;
else if (type == FPType.Zero)
{ case FPType.Zero:
resultBits = SoftFloat16.FPZero(sign); resultBits = SoftFloat16.FPZero(sign);
} break;
else
{ default:
resultBits = SoftFloat16.FPRoundCv(real, context); resultBits = SoftFloat16.FPRoundCv(real, context);
break;
} }
return resultBits; return resultBits;
@ -1056,16 +1059,15 @@ namespace ARMeilleure.Instructions
{ {
if (value1 > value2) if (value1 > value2)
{ {
if (type1 == FPType.Infinity) switch (type1)
{ {
case FPType.Infinity:
result = FPInfinity(sign1); result = FPInfinity(sign1);
} break;
else if (type1 == FPType.Zero) case FPType.Zero:
{
result = FPZero(sign1 && sign2); result = FPZero(sign1 && sign2);
} break;
else default:
{
result = value1; result = value1;
if ((fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result)) if ((fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
@ -1074,20 +1076,20 @@ namespace ARMeilleure.Instructions
result = FPZero(result < 0f); result = FPZero(result < 0f);
} }
break;
} }
} }
else else
{ {
if (type2 == FPType.Infinity) switch (type2)
{ {
case FPType.Infinity:
result = FPInfinity(sign2); result = FPInfinity(sign2);
} break;
else if (type2 == FPType.Zero) case FPType.Zero:
{
result = FPZero(sign1 && sign2); result = FPZero(sign1 && sign2);
} break;
else default:
{
result = value2; result = value2;
if ((fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result)) if ((fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
@ -1096,6 +1098,7 @@ namespace ARMeilleure.Instructions
result = FPZero(result < 0f); result = FPZero(result < 0f);
} }
break;
} }
} }
} }
@ -1147,16 +1150,15 @@ namespace ARMeilleure.Instructions
{ {
if (value1 < value2) if (value1 < value2)
{ {
if (type1 == FPType.Infinity) switch (type1)
{ {
case FPType.Infinity:
result = FPInfinity(sign1); result = FPInfinity(sign1);
} break;
else if (type1 == FPType.Zero) case FPType.Zero:
{
result = FPZero(sign1 || sign2); result = FPZero(sign1 || sign2);
} break;
else default:
{
result = value1; result = value1;
if ((fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result)) if ((fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
@ -1165,20 +1167,20 @@ namespace ARMeilleure.Instructions
result = FPZero(result < 0f); result = FPZero(result < 0f);
} }
break;
} }
} }
else else
{ {
if (type2 == FPType.Infinity) switch (type2)
{ {
case FPType.Infinity:
result = FPInfinity(sign2); result = FPInfinity(sign2);
} break;
else if (type2 == FPType.Zero) case FPType.Zero:
{
result = FPZero(sign1 || sign2); result = FPZero(sign1 || sign2);
} break;
else default:
{
result = value2; result = value2;
if ((fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result)) if ((fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
@ -1187,6 +1189,7 @@ namespace ARMeilleure.Instructions
result = FPZero(result < 0f); result = FPZero(result < 0f);
} }
break;
} }
} }
} }

15
src/ARMeilleure/State/NativeContext.cs
View File

@ -184,35 +184,30 @@ namespace ARMeilleure.State
public unsafe static int GetRegisterOffset(Register reg) public unsafe static int GetRegisterOffset(Register reg)
{ {
if (reg.Type == RegisterType.Integer) switch (reg.Type)
{ {
case RegisterType.Integer:
if ((uint)reg.Index >= RegisterConsts.IntRegsCount) if ((uint)reg.Index >= RegisterConsts.IntRegsCount)
{ {
throw new ArgumentException("Invalid register."); throw new ArgumentException("Invalid register.");
} }
return StorageOffset(ref _dummyStorage, ref _dummyStorage.X[reg.Index]); return StorageOffset(ref _dummyStorage, ref _dummyStorage.X[reg.Index]);
} case RegisterType.Vector:
else if (reg.Type == RegisterType.Vector)
{
if ((uint)reg.Index >= RegisterConsts.VecRegsCount) if ((uint)reg.Index >= RegisterConsts.VecRegsCount)
{ {
throw new ArgumentException("Invalid register."); throw new ArgumentException("Invalid register.");
} }
return StorageOffset(ref _dummyStorage, ref _dummyStorage.V[reg.Index * 2]); return StorageOffset(ref _dummyStorage, ref _dummyStorage.V[reg.Index * 2]);
} case RegisterType.Flag:
else if (reg.Type == RegisterType.Flag)
{
if ((uint)reg.Index >= RegisterConsts.FlagsCount) if ((uint)reg.Index >= RegisterConsts.FlagsCount)
{ {
throw new ArgumentException("Invalid register."); throw new ArgumentException("Invalid register.");
} }
return StorageOffset(ref _dummyStorage, ref _dummyStorage.Flags[reg.Index]); return StorageOffset(ref _dummyStorage, ref _dummyStorage.Flags[reg.Index]);
} default: // case RegisterType.FpFlag
else /* if (reg.Type == RegisterType.FpFlag) */
{
if ((uint)reg.Index >= RegisterConsts.FpFlagsCount) if ((uint)reg.Index >= RegisterConsts.FpFlagsCount)
{ {
throw new ArgumentException("Invalid register."); throw new ArgumentException("Invalid register.");

14
src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs
View File

@ -137,20 +137,20 @@ namespace ARMeilleure.Translation.Cache
Debug.Assert(allocSize % 8 == 0); Debug.Assert(allocSize % 8 == 0);
if (allocSize <= 128) switch (allocSize)
{ {
case <= 128:
_unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocSmall, entry.PrologOffset, (allocSize / 8) - 1); _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocSmall, entry.PrologOffset, (allocSize / 8) - 1);
} break;
else if (allocSize <= 0x7FFF8) case <= 0x7FFF8:
{
_unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 0); _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 0);
_unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize / 8); _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize / 8);
} break;
else default:
{
_unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 1); _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 1);
_unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 0); _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 0);
_unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 16); _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 16);
break;
} }
break; break;

44
src/ARMeilleure/Translation/EmitterContext.cs
View File

@ -108,35 +108,35 @@ namespace ARMeilleure.Translation
protected static OperandType GetOperandType(Type type) protected static OperandType GetOperandType(Type type)
{ {
if (type == typeof(bool) || type == typeof(byte) || switch (Type.GetTypeCode(type))
type == typeof(char) || type == typeof(short) ||
type == typeof(int) || type == typeof(sbyte) ||
type == typeof(ushort) || type == typeof(uint))
{ {
case TypeCode.Boolean:
case TypeCode.Byte:
case TypeCode.Char:
case TypeCode.Int16:
case TypeCode.Int32:
case TypeCode.SByte:
case TypeCode.UInt16:
case TypeCode.UInt32:
return OperandType.I32; return OperandType.I32;
}
else if (type == typeof(long) || type == typeof(ulong)) case TypeCode.Int64:
{ case TypeCode.UInt64:
return OperandType.I64; return OperandType.I64;
}
else if (type == typeof(double)) case TypeCode.Double:
{
return OperandType.FP64; return OperandType.FP64;
}
else if (type == typeof(float)) case TypeCode.Single:
{
return OperandType.FP32; return OperandType.FP32;
}
else if (type == typeof(V128)) case TypeCode.Object when type == typeof(V128):
{
return OperandType.V128; return OperandType.V128;
}
else if (type == typeof(void)) case TypeCode.Object when type == typeof(void):
{
return OperandType.None; return OperandType.None;
}
else default:
{
throw new ArgumentException($"Invalid type \"{type.Name}\"."); throw new ArgumentException($"Invalid type \"{type.Name}\".");
} }
} }

26
src/ARMeilleure/Translation/IntervalTree.cs
View File

@ -152,16 +152,15 @@ namespace ARMeilleure.Translation
while (node != null) while (node != null)
{ {
int cmp = key.CompareTo(node.Start); int cmp = key.CompareTo(node.Start);
if (cmp < 0) switch (cmp)
{ {
case < 0:
node = node.Left; node = node.Left;
} break;
else if (cmp > 0) case > 0:
{
node = node.Right; node = node.Right;
} break;
else default:
{
return node; return node;
} }
} }
@ -272,16 +271,15 @@ namespace ARMeilleure.Translation
{ {
parent = node; parent = node;
int cmp = start.CompareTo(node.Start); int cmp = start.CompareTo(node.Start);
if (cmp < 0) switch (cmp)
{ {
case < 0:
node = node.Left; node = node.Left;
} break;
else if (cmp > 0) case > 0:
{
node = node.Right; node = node.Right;
} break;
else default:
{
outNode = node; outNode = node;
if (updateFactoryCallback != null) if (updateFactoryCallback != null)

11
src/ARMeilleure/Translation/PTC/Ptc.cs
View File

@ -977,26 +977,23 @@ namespace ARMeilleure.Translation.PTC
private static FeatureInfo GetFeatureInfo() private static FeatureInfo GetFeatureInfo()
{ {
if (RuntimeInformation.ProcessArchitecture == Architecture.Arm64) switch (RuntimeInformation.ProcessArchitecture)
{ {
case Architecture.Arm64:
return new FeatureInfo( return new FeatureInfo(
(ulong)Arm64HardwareCapabilities.LinuxFeatureInfoHwCap, (ulong)Arm64HardwareCapabilities.LinuxFeatureInfoHwCap,
(ulong)Arm64HardwareCapabilities.LinuxFeatureInfoHwCap2, (ulong)Arm64HardwareCapabilities.LinuxFeatureInfoHwCap2,
(ulong)Arm64HardwareCapabilities.MacOsFeatureInfo, (ulong)Arm64HardwareCapabilities.MacOsFeatureInfo,
0, 0,
0); 0);
} case Architecture.X64:
else if (RuntimeInformation.ProcessArchitecture == Architecture.X64)
{
return new FeatureInfo( return new FeatureInfo(
(ulong)X86HardwareCapabilities.FeatureInfo1Ecx, (ulong)X86HardwareCapabilities.FeatureInfo1Ecx,
(ulong)X86HardwareCapabilities.FeatureInfo1Edx, (ulong)X86HardwareCapabilities.FeatureInfo1Edx,
(ulong)X86HardwareCapabilities.FeatureInfo7Ebx, (ulong)X86HardwareCapabilities.FeatureInfo7Ebx,
(ulong)X86HardwareCapabilities.FeatureInfo7Ecx, (ulong)X86HardwareCapabilities.FeatureInfo7Ecx,
(ulong)X86HardwareCapabilities.Xcr0InfoEax); (ulong)X86HardwareCapabilities.Xcr0InfoEax);
} default:
else
{
return new FeatureInfo(0, 0, 0, 0, 0); return new FeatureInfo(0, 0, 0, 0, 0);
} }
} }

19
src/ARMeilleure/Translation/SsaConstruction.cs
View File

@ -244,21 +244,20 @@ namespace ARMeilleure.Translation
{ {
Register reg = operand.GetRegister(); Register reg = operand.GetRegister();
if (reg.Type == RegisterType.Integer) switch (reg.Type)
{ {
case RegisterType.Integer:
result = reg.Index; result = reg.Index;
} break;
else if (reg.Type == RegisterType.Vector) case RegisterType.Vector:
{
result = RegisterConsts.IntRegsCount + reg.Index; result = RegisterConsts.IntRegsCount + reg.Index;
} break;
else if (reg.Type == RegisterType.Flag) case RegisterType.Flag:
{
result = RegisterConsts.IntAndVecRegsCount + reg.Index; result = RegisterConsts.IntAndVecRegsCount + reg.Index;
} break;
else /* if (reg.Type == RegisterType.FpFlag) */ default: // case RegisterType.FpFlag
{
result = RegisterConsts.FpFlagsOffset + reg.Index; result = RegisterConsts.FpFlagsOffset + reg.Index;
break;
} }
return true; return true;